? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14042b/d mc14042b quad transparent latch the mc14042b quad transparent latch is constructed with mos pchannel and nchannel enhancement mode devices in a single monolithic structure. each latch has a separate data input, but all four latches share a common clock. the clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. information present at the data input is transferred to outputs q and q during the clock level which is determined by the polarity input. when the polarity input is in the logic a0o state, data is transferred during the low clock level, and when the polarity input is in the logic a1o state the transfer occurs during the high clock level. ? buffered data inputs ? common clock ? clock polarity control ? q and q outputs ? double diode input protection ? supply voltage range = 3.0 vdc to 1 8 vdc ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 3.) 500 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14042bcp pdip16 2000/box mc14042bd soic16 2400/box mc14042bdr2 soic16 2500/tape & reel 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. marking diagrams 1 16 pdip16 p suffix case 648 mc14042bcp awlyyww soic16 d suffix case 751b 1 16 14042b awlyww soeiaj16 f suffix case 966 1 16 mc14042b alyw mc14042bf soeiaj16 see note 1. mc14042bfel soeiaj16 see note 1. mc14042bfr1 soeiaj16 see note 1. mc14042bfr2 soeiaj16 see note 1.
mc14042b http://onsemi.com 2 pin assignment truth table 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 q 2 d2 d3 q 3 v dd q 1 q1 q2 d0 q 0 q0 q3 v ss d1 polarity clock clock polarity q 0 0 data 1 0 latch 1 1 data 0 1 latch logic diagram clock polarity v dd = pin 16 v ss = pin 8 5 6 4 7 13 14 d3 d2 d1 d0 latch 1 latch 2 latch 3 latch 4 q 2 q 3 q3 q2 q 1 q1 q 0 q0 12 2 3 10 9 11 1 15
mc14042b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) ?????????? ?????????? ???? ???? ??? ??? v dd ????? ????? 55 c ????????? ????????? 25 c ????? ????? 125 c ??? ??? ?????????? ?????????? characteristic ???? ???? symbol ??? ??? v dd vdc ??? ??? min ??? ??? max ???? ???? min ??? ??? typ (4.) ???? ???? max ??? ??? min ??? ??? max ??? ??? unit ?????????? ? ???????? ? ?????????? output voltage a0o level v in = v dd or 0 ???? ? ?? ? ???? v ol ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? e e e ??? ? ? ? ??? 0.05 0.05 0.05 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 0 0 0 ???? ? ?? ? ???? 0.05 0.05 0.05 ??? ? ? ? ??? e e e ??? ? ? ? ??? 0.05 0.05 0.05 ??? ? ? ? ??? vdc ?????????? ? ???????? ? ?????????? a1o level v in = 0 or v dd ???? ? ?? ? ???? v oh ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? 4.95 9.95 14.95 ??? ? ? ? ??? e e e ???? ? ?? ? ???? 4.95 9.95 14.95 ??? ? ? ? ??? 5.0 10 15 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 4.95 9.95 14.95 ??? ? ? ? ??? e e e ??? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ???? ? ?? ? ? ?? ? ???? v il ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? 1.5 3.0 4.0 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 2.25 4.50 6.75 ???? ? ?? ? ? ?? ? ???? 1.5 3.0 4.0 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? 1.5 3.0 4.0 ??? ? ? ? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) ???? ? ?? ? ? ?? ? ???? v ih ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? 3.5 7.0 11 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 3.5 7.0 11 ??? ? ? ? ? ? ? ??? 2.75 5.50 8.25 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 3.5 7.0 11 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ? ???????? ? ?????????? output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) ???? ? ?? ? ? ?? ? ? ?? ? ???? i oh ??? ? ? ? ? ? ? ? ? ? ??? 5.0 5.0 10 15 ??? ? ? ? ? ? ? ? ? ? ??? 3.0 0.64 1.6 4.2 ??? ? ? ? ? ? ? ? ? ? ??? e e e e ???? ? ?? ? ? ?? ? ? ?? ? ???? 2.4 0.51 1.3 3.4 ??? ? ? ? ? ? ? ? ? ? ??? 4.2 0.88 2.25 8.8 ???? ? ?? ? ? ?? ? ? ?? ? ???? e e e e ??? ? ? ? ? ? ? ? ? ? ??? 1.7 0.36 0.9 2.4 ??? ? ? ? ? ? ? ? ? ? ??? e e e e ??? ? ? ? ? ? ? ? ? ? ??? madc ?????????? ? ???????? ? ?????????? (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) ???? ? ?? ? ???? i ol ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? 0.64 1.6 4.2 ??? ? ? ? ??? e e e ???? ? ?? ? ???? 0.51 1.3 3.4 ??? ? ? ? ??? 0.88 2.25 8.8 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 0.36 0.9 2.4 ??? ? ? ? ??? e e e ??? ? ? ? ??? madc ?????????? ?????????? input current ???? ???? i in ??? ??? 15 ??? ??? e ??? ??? 0.1 ???? ???? e ??? ??? 0.00001 ???? ???? 0.1 ??? ??? e ??? ??? 1.0 ??? ??? m adc ?????????? ? ???????? ? ?????????? input capacitance (v in = 0) ???? ? ?? ? ???? c in ??? ? ? ? ??? e ??? ? ? ? ??? e ??? ? ? ? ??? e ???? ? ?? ? ???? e ??? ? ? ? ??? 5.0 ???? ? ?? ? ???? 7.5 ??? ? ? ? ??? e ??? ? ? ? ??? e ??? ? ? ? ??? pf ?????????? ? ???????? ? ?????????? quiescent current (per package) ???? ? ?? ? ???? i dd ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? e e e ??? ? ? ? ??? 1.0 2.0 4.0 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 0.002 0.004 0.006 ???? ? ?? ? ???? 1.0 2.0 4.0 ??? ? ? ? ??? e e e ??? ? ? ? ??? 30 60 120 ??? ? ? ? ??? m adc ?????????? ? ???????? ? ? ???????? ? ? ???????? ? ?????????? total supply current (5.) (6.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs all buffers switching) ???? ? ?? ? ? ?? ? ? ?? ? ???? i t ??? ? ? ? ? ? ? ? ? ? ??? 5.0 10 15 ????????????????? ? ??????????????? ? ? ??????????????? ? ? ??????????????? ? ????????????????? i t = (1.0 m a/khz) f + i dd i t = (2.0 m a/khz) f + i dd i t = (3.0 m a/khz) f + i dd ??? ? ? ? ? ? ? ? ? ? ??? m adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.004.
mc14042b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (7.) (c l = 50 pf, t a = 25 c) ??????????????? ??????????????? characteristic ????? ????? symbol ???? ???? v dd ???? ???? min ???? ???? typ (8.) ???? ???? max ??? ??? unit ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns ????? ? ??? ? ? ??? ? ????? t tlh , t thl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 100 50 40 ???? ? ?? ? ? ?? ? ???? 200 100 80 ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? propagation delay time, d to q, q t plh , t phl = (1.7 ns/pf) c l + 135 ns t plh , t phl = (0.66 ns/pf) c l + 57 ns t plh , t phl = (0.5 ns/pf) c l + 35 ns ????? ? ??? ? ? ??? ? ????? t plh , t phl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 220 90 60 ???? ? ?? ? ? ?? ? ???? 440 180 120 ??? ? ? ? ? ? ? ??? no ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? propagation delay time, clock to q, q t plh , t phl = (1.7 ns/pf) c l + 135 ns t plh , t phl = (0.66 ns/pf) c l + 57 ns t plh , t phl = (0.5 ns/pf) c l + 35 ns ????? ? ??? ? ? ??? ? ????? t plh , t phl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 220 90 60 ???? ? ?? ? ? ?? ? ???? 440 180 120 ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? clock pulse width ????? ? ??? ? ? ??? ? ????? t wh ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? 300 100 80 ???? ? ?? ? ? ?? ? ???? 150 50 40 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? clock pulse rise and fall time ????? ? ??? ? ? ??? ? ????? t tlh , t thl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 15 5.0 4.0 ??? ? ? ? ? ? ? ??? m s ??????????????? ? ????????????? ? ??????????????? hold time ????? ? ??? ? ????? t h ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? 100 50 40 ???? ? ?? ? ???? 50 25 20 ???? ? ?? ? ???? e e e ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? setup time ????? ? ??? ? ? ??? ? ????? t su ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? 50 30 25 ???? ? ?? ? ? ?? ? ???? 0 0 0 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. figure 1. ac and power dissipation test circuit and timing diagram (data to output) v dd v ss pulse generator 1 16 5 6 4 7 13 14 clock polarity d0 d1 d2 d3 q 3 q3 q 2 q2 q 1 q1 q 0 q0 15 1 12 11 9 10 3 2 8 for power dissipation test, each output is loaded with capacitance c l . 1 f 20 ns 20 ns data input q output q output t plh t phl t tlh t thl t tlh t thl 90% 50% 10% 50% 90% 10% 90% 10% 50% t phl
mc14042b http://onsemi.com 5 figure 2. ac test circuit and timing diagram (clock to output) note: c l connected to output under test. 20* ns 20 ns 90% 10% pulse generator 1 pulse generator 2 v dd 16 5 6 4 7 13 14 clock polarity d0 d1 d2 d3 q 3 q3 q 2 q2 q 1 q1 q 0 q0 v ss 8 15 1 12 11 9 10 3 2 50% t wh 20 ns 90% 50% t su t h t plh 90% 50% 10% clock input p.g. 1 data input p.g. 2 q output *input clock rise time is 20 ns except for maximum rise time test.
mc14042b http://onsemi.com 6 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic16 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc14042b http://onsemi.com 7 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o
mc14042b http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14042b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk
|
